FIG. 5 shows, in cross-section, a conventional hybrid infrared detecting array. Semiconductor substrate 1 contains signal processing circuitry. A p-type semiconductor substrate 30 includes photodetecting elements for converting incident infrared light into electrical charges, i.e., electrical signals. Spaced apart n-type regions 32 are formed in the substrate 30 by diffusion, establishing pn junction photodiodes between the substrate 30 and the regions 32. Semiconductor substrate 1 may be silicon or gallium arsenide containing signal processing circuitry 31. The signal processing circuitry 31 includes circuitry for storing the electrical charges, i.e., the signal charges, produced by the photodiodes in response to incident infrared light, and charges, such as a charge coupled device (CCD), to external circuitry. A plurality of electrodes 50 are disposed between and join the substrates 1 and 30, electrically interconnecting the photodiodes and the signal processing circuitry 31.
Infrared detectors, particularly those having a desired response in the 10 micron wavelength band, e.g., 8 to 10.5 microns, exhibit particular technical problems. A consistent problem is the presence of relatively high intensity background radiation, meaning that the desired signal or image, in the case of a two-dimensional array, has low contrast and the suppression of noise must be given particular attention.
Black body radiation at a temperature of 300.degree. K. has an intensity versus wavelength distribution as shown in FIG. 6(a). That distribution, i.e., the background, includes a peak at wavelengths around 10 microns resulting from a combination of the energy and quantity distributions of photons as a function of wavelength.
The energy of a photon and its wavelength are related by: EQU E=1.24/.lambda.
where E is the energy of the photon in electron volts (eV) and .lambda. is the wavelength of the photon in microns. The relative quantity of photons produced by the radiating black body is related to photon energy by: EQU N=I/E
where I is the energy of the incident light in electron volts (eV), N is the number of photons in the incident light, and E is the energy of the photons in electron volts (eV). While the energy of a photon having a wavelength of 3 to 5 microns is larger than the energy of a photon having a wavelength from 8 to 10.5 microns, the quantity of photons emitted from a black body at 300.degree. K. having wavelengths from 8 to 10.5 microns is larger than the number of photons emitted with wavelengths from 3 to 5 microns. For example, the flux of photons having wavelengths from 8 to 10.5 microns radiated by a black body at 300.degree. K. is about 3.6.times.10.sup.17 photons/cm.sup.2 s, about thirty times as many photons as are radiated in the 3 to 5 micron wavelength range. Thus, the peak intensity of infrared radiation from a black body at 300.degree. K. occurs at about a 10 micron wavelength.
These wavelength-sensitive intensity differences mean that the contrast of an infrared signal or image being sensed, that is, the ratio of the signal component S to the background signal B of the incident rays in the 8 to 10.5 micron wavelength band (FIG. 6(c)) is smaller than that in the 3 to 5 micron wavelength band (FIG. 6(b)) at 300.degree. K. Quantitatively, the contrast of an infrared signal or image in the 8 to 10.5 micron wavelength band is about one-half of that of an image in the 3 to 5 micron wavelength band. To improve the signal-to-noise ratio in the 8 to 10.5 micron wavelength, "charge skimming" is employed.
A hybrid infrared detector employing the charge skimming method is described in "Hybrid Infrared Focal-Plane Arrays" by Chow et al, Volume ED-29, Number 1, January, 1982, of the IEEE Transactions on Electron Devices. FIGS. 7(a) and 7(b) schematically show the charge transfer potential well structure of a light detecting element and a schematic geometric structure of a two-dimensional infrared detector array, respectively, of the types described by Chow et al. In FIG. 7(a), a p-type semiconductor substrate 100 includes signal processing circuitry. An n.sup.+ -type connection region 2 is disposed in the substrate 100. A photodiode 20 for detecting incident infrared light includes a cathode, i.e, an n-type region, connected with the n.sup.+ -type region 2, and an anode, i.e., a p-type region that is grounded.
A charge storage electrode 12, V.sub.STORE, produces a potential well 3 for storing signal charges in the p-type semiconductor substrate 100. A gate electrode 11, V.sub.T, controls the introduction of the signal charges from the photodiode 20 into the potential well 3. A dividing electrode 13, V.sub.PART, divides the potential well 3 and the signal charges stored in the potential well 3 into potential well parts 3a and 3b containing the divided charges. A skimming electrode 14, V.sub.SKIM, controls the transfer of charges from the potential well part 3b to a potential well 4. A CCD electrode 15 produces the potential well 4 and supplies the signal charges stored in that well 4 to a CCD. A field effect transistor (FET) 5 empties charges from potential well 3, resetting the circuitry, and includes a gate electrode 16, V.sub.BLOOM, and a drain electrode 17, V.sub.DRAIN.
In FIG. 7(b), a two-dimensional array of photodetectors and the associated signal processing circuity of the type forming the light detecting element illustrated in FIG. 7(a) is schematically shown. In FIGS. 7(a) and 7(b) and in all other figures, the same elements are given the same reference numbers. FIG. 7(b) includes a two-dimensional 5 by 5 array of light detecting elements. The array includes five columns of light detecting elements with five light detecting elements in each column. Charges from the elements in each column are transferred along separate columns of CCDs and are ultimately collected in a single row 36 of CCDs. The CCDs in row 36 pass the collected signal along to extenral circuitry so that a two-dimensional detected image can be represented by the collected charges.
The operation of the signal processing circuitry of FIG. 7(a) is illustrated in FIGS. 9(a) through 9(d). In the initial state, a relatively high voltage is applied to the storage electrode 12 to produce the potential well 3 in the substrate 100 opposite the electrode 12. A still higher voltage is next applied to the gate electrode 11 to produce an inversion layer at the surface of the substrate 100 opposite the gate electrode 11. The inversion layer forms a conducting channel so that signal charges generated by the photodiode 20 flow from n.sup.+ -type connection region 2 into the charge storage potential well 3 and are stored there, as illustrated in FIG. 9(b).
Subsequently, a relatively low voltage is applied to the dividing electrode 13, dividing the potential well 3 into parts 3a and 3b. The charges stored in the potential well 3 are also separated into two parts by the division of the well 3. Some of the charges remain in the well part 3a and others are stored in the well part 3b. Without the division of stored signal charges, the quantity of charges from potential well 3 might exceed the storage capacity of and overflow the potential well 4 of the CCD when transferred from the well 3. By dividing the potential well 3 and the charges stored in it, only charges from the charge storage well part 3b are transferred into the potential well 4, as indicated in FIG. 9(c).
In order to transfer the charges from the potential well part 3b to the potential well 4, a relatively high voltage is applied to the skimming electrode 14. The charges in the potential well part 3b having energies exceeding the potential barrier between the potential well part 3b and the potential well 4 flow into the potential well 4 opposite the CCD electrode 15. The height of that potential barrier is controlled by the voltage applied to the skimming electrode 14 relative to the voltages on the electrodes 12 and 15. Thus, the signal is "skimmed" so that only the signal charges representing a desired image and a portion of the background reach the potential well 4. This charge flow is illustrated in FIG. 9(d).
Finally, a relatively high voltage is applied to the dividing electrode 13 to remove the potential barrier between the well parts 3a and 3b. Then, a voltage is applied to the gate electrode 16 to turn on FET 5 and thereby drain the remaining charges from the potential well 3 via the drain electrode 17.
The charge storage capacity of the prior art infrared detector described cannot be increased easily. Generally, in order to enhance the signal-to-noise ratio it is only necessary to increase the integration time, i.e., the time during which charges from the photodetector 20 are collected before their transfer from n.sup.+ -type region 2 to the potential well 4. The signal-to-noise ratio is improved in proportion to the square root of the integration time. FIG. 8(b) shows a comparison between the amount of charge stored during a short integration time, example A, and a long integration time, example B. Although a longer integration time provides improved results, in the conventional detectors the charge storage capacity of the wells can be increased only by increasing the area of the electrodes, i.e., the size of the circuitry on the substrate. Increased substrate circuitry size is undesirable because substrate area is limited. In addition, image resolution is decreased when the electrode area is increased because the area available for photodiodes is reduced so that the density of the photodiodes is reduced.
A structure like that schematically shown in FIG. 10 could be adopted for hybrid infrared detector arrays. In FIG. 10, the substrate 100 has a larger size on the signal processing circuitry side than the photoelectric conversion substrate 30. The substrates 30 and 100 are electrically connected with each other by connecting electrodes 50. However, the connecting electrodes 50 are required to be obliquely disposed relative to the substrates because of the different sizes of the substrates, making their production quite difficult. Moreover, by enlarging the signal processing circuitry substrate 100, the charge transfer distances in the charge transfer circuitry are increased, limiting the speed of operation.